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CS5461A
DIGITAL CHARACTERISTICS
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Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Internal Gate Oscillator (Note 10) MCLK
2.5
40
40
4.096
-
20
60
60
MHz
%
%
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
(Voltage Channel, 60 Hz)
DCLK = MCLK/K
-2.8
-
-
DCLK/8
+2.8
-
°
Hz
Digital Filter Output Word Rate
(Both Channels)
OWR
-
DCLK/1024
-
Hz
High-pass Filter Corner Frequency
Full Scale Calibration Range ( Referred to Input )
Channel-to-channel Time-shift Error
-3 dB
-
25
0.5
-
1.0
-
100
Hz
%F.S.
μs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IH
0.6 VD+
(VD+) - 0.5
0.8 ? VD+
-
-
-
-
-
-
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IL
-
-
-
-
-
-
0.8
1.5
0.2 ? VD+
V
V
V
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V IL
-
-
-
-
-
-
0.48
0.3
0.2 ? VD+
V
V
V
High-level Output Voltage
Low-level Output Voltage
Input Leakage Current
3-state Leakage Current
Digital Output Pin Capacitance
I out = +5 mA
I out = -5 mA
(Note 15)
V OH
V OL
I in
I OZ
C out
(VD+) - 1.0
-
-
-
-
-
-
±1
-
5
-
0.4
±10
±10
-
V
V
μA
μA
pF
Notes: 9. All measurements performed under static conditions.
10.
11.
12.
13.
14.
15.
DS661F3
If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
The frequency of CPUCLK is equal to MCLK.
The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.
Configuration Register bits PC[6:0] are set to “0000000”.
The MODE pin is pulled low by an internal resistor.
9
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